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t TDMC
TDMxTCLK
t TDMCH
t TDMDHOV
t TDMCL
t TDMDHOZ
TDMxTDAT
t TDMDHOX
t TDMSHOV
t TDMHOX
t TDMSHOX
TDMxTSYN
Figure 20. TDM Output Signals
Note:
2.6.8
For some TDM modes, transmit data is output on other pins. This timing is also valid for those pins. See the
MSC8144 Reference Manual
UART Timing
Table 38. UART Timing
Characteristics
URXD and UTXD inputs high/low duration
Symbol
T UREFCLK
Expression
16 × T REFCLK
Min
160
Max
—
Unit
ns
Note:
T UREFCLK = T REFCLK is guaranteed by design.
Figure 21 shows the UART input AC timing
UTXD, URXD
inputs
T UREFCLK
Figure 21. UART Input Timing
Figure 22 shows the UART output AC timing
UTXD output
T UREFCLK
T UREFCLK
T UREFCLK
Figure 22. UART Output Timing
MSC8144 Quad Core Digital Signal Processor Data Sheet, Rev. 16
Freescale Semiconductor
53
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